1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus.
2. Related Art
As semiconductor memory devices become more highly integrated and high-performing, efforts to reduce the chip area are taking place with respect to semiconductor memory device manufacturing processes and circuit arrangement methods (i.e., layout), as well as in the area of circuits.
FIG. 1 is a block diagram schematically illustrating a conventional semiconductor memory apparatus.
Referring to FIG. 1, the conventional semiconductor memory apparatus 10 includes an impedance calibration block (a ZQ calibration block) 12. The impedance calibration block 12 generates first and second code signals (PCODE<0:M-1> and NCODE<0:M-1>, respectively), which vary depending on PVT (process, voltage and temperature) conditions, and calibrates termination resistance values of input/output blocks 14 by using first code signals and second code signals generated as a result of impedance calibration. Since the first code signals PCODE<0:M-1> and the second code signals NCODE<0:M-1> have a predetermined number of bits, a plurality of lines are required.
Meanwhile, the semiconductor memory apparatus 10 has lines for a plurality of test mode signals TM<0:N-1> used for testing a chip, in addition to lines for the first code signals PCODE<0:M-1> and the second code signals NCODE<0:M-1>. Accordingly, the semiconductor memory apparatus 10 uses numerous global lines, resulting in the problem of increased chip area.